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Samsung Demonstrates 3D Stacked FETs with Triple Nanosheet Channels at 42nm

36 points by its_ajseven ago | 9 comments

RicoElectrico |next |previous [-]

How about heat? Seems these days it's the heat above everything else that's the issue. And more density would only aggravate it.

juancn |root |parent |next [-]

That's always an issue, but the industry seems to be moving away from 2D circuits.

Reducing trace length seems to be the way forward for faster/larger circuits. Signal propagation time on-die is becoming an issue.

Things like Huawei's Logic folding, or TSVs, and so on, attack the issue by reducing signal travel time.

This looks like another building block in that direction.

There's also some push at cooling chips from both sides.

arein3 |root |parent |next |previous [-]

What you loose in heat you gain in speed caused by proximity. Perhaps this will allow for lower voltage and thus less heat.

deepsun |root |parent |next |previous [-]

If heat is produced by conductors resistance then shorter paths would lead to less heat produced.

ben_w |root |parent [-]

I'm not certain (never did hardware), but I thought the transistor switching cost was one of the bigger sources of energy loss, not internal conductor resistance between transistors?

deepsun |root |parent [-]

Makes sense, I also doubt that they haven't minimized resistance to minimum already.

ortusdux |root |parent |previous [-]

I wonder if the proposed CPU/GPU laser cooling technique that was on here a few days ago would penetrate the Si layers?

https://news.ycombinator.com/item?id=48510375

armitron |next |previous [-]

This seems like it could accelerate the transition to sub-1nm nodes (previously projected to mid 2030s), maybe by the end of this decade.

its_ajseven |previous [-]

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